In this highly technical 2-3 hour online JTAG training course, our experts will provide you with a hands-on introduction to JTAG boundary scan, using real hardware.

You will learn to create and run diagnostic tests from your PC without needing physical access or custom functional test development. During the workshop exercises you will have remote access to XJTAG’s full Test Developer Pro system connected to demo hardware.

All you need is a web browser. No prior knowledge of JTAG is required.

Who should attend? Engineers working in PCB design, development, test and manufacturing.

➡️ Wednesday, 19 November 2025

*Seats are limited

In this free, 60-minute webinar, Vittorio Serra from Lauterbach and Curt Hillier from NXP Semiconductors demonstrate how Lauterbach’s TRACE32® tools integrate with NXP’s S32 platforms to streamline software-defined vehicle (SDV) development using virtual prototypes and remote access.

Key topics and takeaways:

• Gain insights into cloud-based debugging: Eliminate hardware dependency with remote access to virtual S32 targets.
• Explore optimized workflows for SDVs: Tailored for zonal, central, domain and ADAS architectures.
• Discover advanced debugging & profiling: Unlock deep performance insights with TRACE32’s debug and real-time trace tools.
• Learn about seamless integration: Accelerate development with pre-integrated stacks and CI/CD compatibility.

➡️ Thursday, 13 November 2025

Can’t join live? Register to receive the slides and recording afterward

Join us for an in-depth webinar on the Lauterbach Mixed Signal Probe.Learn how it delivers a single, powerful solution for analyzing both digital and analog signals, and how to seamlessly trace signals and correlate them with code execution throughout development and testing.

Agenda:

• Demo Setup Hardware & Software: A detailed look at the setup, including utrace/PowerDebug, Nucleo H7S3L8, and the BME680 (I2C source). 
• Wiring Guide: Step-by-step instructions for correct hardware connections. 
• Configuration: Learn how to use the CMM file and commands for optimal setup.

Live Demo

• Power Measurements: Real-time current, voltage, and power measurements of the BME680 sensor. 
• Register Analysis: Observe the interaction between registers (Tx/Rx) and Interrupt Service Routines (ISRs) versus signals on the I2C bus. 
• Waveform Visualization: Analyze SCL/SDA waveforms on the I2C bus. 
• Troubleshooting: Identify and correct issues like incorrect pull-up resistor configurations (waveform/signal level analysis).

Wrap-up

• Broader Applications: Mixed Signal Probe usage in other communication protocols & measurements. 
• Quick Start Guide: A handy cheat sheet for getting started quickly with the Lauterbach Mixed Signal Probe. 
• Q&A Session

➡️ Thursday, 6 November 2025

Can’t join live? Register to receive the slides and recording afterward

The EU Cyber Resilience Act (CRA) sets new expectations for embedded products - from secure design to traceable evidence. In this session, we’ll show how to turn CRA requirements into practical architecture decisions, manage updates safely, and prepare the minimal proof needed for CE compliance and audits. You’ll leave with a clear view of what to design, document, and verify to make your embedded products CRA-ready.

Objective

• Understand what the CRA expects from embedded products and teams.
• Turn requirements into architectural decisions (boot, keys, updates, SBOM flow)
• Know the minimal evidence you need for CE/conformity and audits.
• Explore solutions to comply with the CRA.

Agenda:

Why these matters

• Overview of PDE and product classification
• What’s in scope for embedded; typical pitfalls we see.
• How this relates to CE/conformity and other EU regs (NIS2/Cybersecurity Act).

Secure-by-Design: decisions you lock in early

• Threat model “lite” that drives architecture.
• Root of trust & key management options (TPM/SE vs. MCU features).
• Partitioning & least privilege (boot chain, services, comms).
• What to write down now so it becomes evidence later.

Evidence by architecture

• Map requirements → artifacts: update policy, vuln-handling procedure, SBOM, release notes, EoL/patch policy
• ARM security features that help
• TF-M benefits
• RTOSs and Zephyr integration: TF-M (Secure) + Zephyr app (Non-Secure), MCUboot

Updates without bricking devices

• Trust chain for updates: signing, versioning, rollback, recovery paths.
• Field constraints: bandwidth, power, storage; how to choose a strategy.
• SBOM flow through the pipeline (Yocto/Zephyr examples), vulnerability handling.

Q&A

➡️ Monday, 8 December 2025

Can’t join live? Register to receive the slides and recording afterward